Computer central processors typically include a basic operations execution unit which performs much of the routine processing including adding, subtracting, logical combining and other logical manipulation of information words. The basic operations execution unit may also perform all multiplication and division, but the performance of the central processor is markedly enhanced if more complex calculations, such as floating point operations, are assigned to a co-processor.
Central processor calculation units include a number of dedicated registers including an accumulator register (often called the "A register") and a supplementary accumulator register (often called the "Q register") which may be concatenated with the A register to hold a double word information operand (or two single word operands) or result. Typically, there are a number of other dedicated registers (often called the "X" registers) which serve as address modification registers. For convenience, these dedicated registers will be designated as AQX registers below; however, those skilled in the art will understand that they may have different designations in various specific central processors.
In the case of a central processor incorporating a co-processor as well as a basic operations execution unit, it has been the practice to provide each calculation unit with its own pair of A-Q registers. If the basic operations execution unit decodes an instruction which has been predetermined to be better handled by the co-processor, in part or in whole, the task is assigned to the co-processor by the basic operations execution unit which also forwards to the co-processor the contents of its A and Q registers for placement into the corresponding registers in the co-processor. When the co-processor completes its assigned calculation, it signals the basic operations execution unit accordingly, and the control circuitry in the two units coordinates the transfer of the results from the A and Q registers in the co-processor to the A and Q registers in the basic operations execution unit.
While it is a great advantage to include a co-processor in a central processor that must routinely carry out substantial extended calculations, the necessary transfer of data between the respective A and Q registers of the basic operations execution unit and of the co-processor, as described immediately above, "costs" numerous machine cycles which somewhat offsets the speed of performance advantage obtained from the co-processor.
As faster operation of computers has been sought, numerous hardware/firmware features have been employed to achieve that purpose. One widely incorporated feature directed to increasing the speed of operation is pipelining in which the various stages of execution of a series of consecutive machine level instructions are undertaken simultaneously. Thus, during a given time increment, a first stage of a fourth (in order of execution) instruction may be undertaken while a second stage of a third instruction, a third stage of a second instruction and a fourth stage of a first instruction are all undertaken simultaneously.
In a pipelined central processor, the incorporation of a co-processor has a further drawback which also offsets some of the speed advantage obtained thereby. It is necessary to keep track of which A-Q register pair is "correct" and, at times, to stop the pipeline to update one register pair from the other before it can be used.
Those skilled in the art will appreciate that it would be highly desirable to employ a co-processor in a central processor, which may or may not be pipelined, without incurring the offsetting speed penalties resulting from each of the basic operations execution unit and the co-processor employing its own pair of A and Q registers.